Switching losses are a central factor in determining the overall performance of modern power electronics applications. It is crucial to accurately and efficiently estimate these losses since they affect system efficiency and power density. Despite the importance of accurate estimations, there is a lack of a broadly-accepted uniform approach for estimating this important loss mechanism across different semiconductor types, ratings, and vendors which limits the ability of engineers to manage the trade-offs inherent in the design of power electronics. This thesis compares two of the most widely used techniques for estimating switching losses of power semiconductors: continuous converter operation (CCO) and double-pulse testing (DPT). These techniques are evaluated in terms of accuracy, ease of implementation, and metrology considerations. An empirical setup was fabricated to test both techniques on the same platform with minimal changes to the setup between the tests. The same semiconductor was evaluated with both techniques, and the resulting switching loss estimations were then compared. It was found that the CCO technique over-estimates the DUT switching losses by 27.8% on average. This error can likely be attributed to the frequency-dependent losses of the diode, inductor core losses, and the temperature dependence of components. Better agreement between CCO and DPT loss predictions are demonstrated when the frequency-dependent loss of the diode are added to the DPT estimation. This indicates that the CCO method includes additional loss mechanisms and suggests that the results from the DPT technique provide a more accurate estimate of DUT switching losses.