An experimental investigation of an on-chip interconnect fabric using a multiprocessor system-on-chip architecture

Show simple item record

dc.contributor Jackson, Jeff
dc.contributor Woodbury, Keith A.
dc.contributor.advisor Ricks, Kenneth G.
dc.contributor.author Bangal, Priya
dc.date.accessioned 2017-03-01T14:46:14Z
dc.date.available 2017-03-01T14:46:14Z
dc.date.issued 2011
dc.identifier.other u0015_0000001_0000694
dc.identifier.other Bangal_alatus_0004M_10736
dc.identifier.uri https://ir.ua.edu/handle/123456789/1199
dc.description Electronic Thesis or Dissertation
dc.description.abstract Recent advances in technology have made it possible to integrate systems with CPUs, memory units, buses, specialized logic, other digital functions and their interconnections on a single chip, giving rise to the concept of system-on-chip (SoC) architectures. In order to keep up with the incoming data rates of modern applications and to handle concurrent real-world events in real-time, multiprocessor SoC implementations have become necessary. As more processors and peripherals are being integrated on a single chip, providing an efficient and a functionally optimum interconnection has become a major design challenge. The traditional shared-bus-based approach is quite popular in SoC architectures as it is simple, well-understood and easy to implement. However, its scalability is limited, since the bus invariably becomes a bottleneck as more processors are added. Switch-based networks can overcome this bottleneck while providing true concurrency and task-level parallelism, resulting in a higher throughput. However, switch-based networks are complex and consume considerable amounts of logic resources on a chip, thus increasing the cost. Hence, the choice of switch-based networks over a bus-based architecture is an important design consideration in SoC architectures. This choice hinges on the trade-off between design simplicity and low cost vs. high communication bandwidth. This research investigates the logic resource utilization of a switch-based on-chip interconnect to analyze its scalability for multiprocessor systems. It also experimentally demonstrates the true concurrency provided by the interconnect, investigates the arbitration mechanism used, and suggests the use of a real-time operating system (RTOS) as a more effective way of managing on-chip interconnections.
dc.format.extent 135 p.
dc.format.medium electronic
dc.format.mimetype application/pdf
dc.language English
dc.language.iso en_US
dc.publisher University of Alabama Libraries
dc.relation.ispartof The University of Alabama Electronic Theses and Dissertations
dc.relation.ispartof The University of Alabama Libraries Digital Collections
dc.relation.hasversion born digital
dc.rights All rights reserved by the author unless otherwise indicated.
dc.subject.other Computer engineering
dc.subject.other Electrical engineering
dc.title An experimental investigation of an on-chip interconnect fabric using a multiprocessor system-on-chip architecture
dc.type thesis
dc.type text
etdms.degree.department University of Alabama. Dept. of Electrical and Computer Engineering
etdms.degree.discipline Electrical and Computer Engineering
etdms.degree.grantor The University of Alabama
etdms.degree.level master's
etdms.degree.name M.S.


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search DSpace


Browse

My Account