Through-silicon vias (TSVs) have been extensively studied because of their ability to achieve chip stacking for enhanced system performance. The fabrication process is becoming somewhat mature. However, reliability issues need to be addressed in order for an eventual transition from laboratory to production. This dissertation discusses the TSV fabrication process, testing results for TSV reliability investigation of an integration of TSVs and capacitor devices. In our laboratory, vias with tapered sidewalls are formed through a modified Bosch process using deep reactive ion etching (DRIE). Cryogenic etching is also considered as a means to etch vias without sidewall scalloping that is observed for the Bosch process. Vias are lined with silicon dioxide using plasma enhanced chemical vapor deposition (PECVD) followed by a sputter deposited titanium barrier and a copper seed layer before filling by a reverse pulse copper electroplating process. Following attachment of the process wafer to a carrier wafer, the process wafer is thinned from the backside by a combination of mechanical methods and reactive ion etching (RIE). Fabricated vias are subjected to thermal cycling with temperatures ranging from 25 °C to 125 °C. TSVs are shown to be stable with small increases in measured resistance for 200 cycles. In addition, small changes in resistance are observed when vias are held at elevated temperatures for extended periods of time. Integration of decoupling capacitors with TSVs represents a good alternative to conventional 2-D layouts to achieve miniaturization and increased density. Therefore, decoupling capacitors can be brought in close proximity to the active elements, thereby, reducing their parasitic inductance and allowing higher clock rates. In this study, capacitors with anodized tantalum as the dielectric are integrated with TSVs without negatively impacting their operation. The performance of these capacitors was evaluated by measuring resonant frequency, parasitic inductance, and parasitic resistance.