Browsing by Author "Helton, Jared"

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    Comprehensive analysis of filter inductor asymmetry on conducted emissions in buck and boost converters
    (University of Alabama Libraries, 2020) Helton, Jared; Lemmon, Andrew; University of Alabama Tuscaloosa
    Increased edge rates and switching frequencies have led to higher efficiency and increased power density for dc-dc converter topologies utilizing wide band-gap (WBP) devices. These improvements in intended behavior come with a cost in the form of elevated EMI profiles and higher magnitude CM currents, which cause challenges in fielded systems. Therefore, there is an increasing need to model the CM behavior for these systems and provide efficient EMI mitigation techniques. A method to decompose a system’s mixed-mode (MM) behavior into its differential-mode (DM) and common-mode (CM) behavior is utilized in this thesis. This thesis analyzes the role of filter inductor asymmetry in decreasing emissions in common dc-dc converters while preserving the intended behavior of these systems. The proposed decomposition method is applied to buck and boost converters. This method produces common-mode equivalent models (CEMs) that provide simplified expressions for the CM behavior of systems. CEMs are developed for both simplified and practical implementations of the considered topologies. Analysis of these CEMs reveals that both converters demonstrate similar CM behavior trends for the simplified models but exhibit different CM behavior trends for the practical models. Two prototype buck converters are then utilized to empirically validate the CEMs for this topology. A low-power prototype is utilized to validate the simplified model. This example demonstrates the necessity of considering high-frequency voltage ripple to accurately represent the CM behavior of this topology. A high-power prototype is utilized to validate the practical model. This example demonstrates the sensitivity of a fielded system to unintended couplings with the grounding network.
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    Equivalent Modeling of Medium-Voltage Gate Drive Circuitry
    (University of Alabama Libraries, 2023) Helton, Jared; Lemmon, Andrew N
    There has been a recent increase in the utilization of wide bandgap (WBG) devices in power electronic converter designs. Designs leveraging these devices are capable of achieving high efficiencies and increased power density as compared to more traditional Silicon (Si) based converters. The same behaviors responsible for the increase in utilization of WBG devices also cause an increase in electromagnetic interference (EMI) and potential false turn-on events. The high edge rates for the devices can induce significant current through the gate-to-drain capacitor, causing disturbance voltages across the gate-to-source nodes. The gate-to-source voltage controls whether the device turns on or off, and the disturbance voltages can be severe enough to cause shoot through or even cause the device to fail. Additionally, the more spectrally rich profiles for WBG devices creates challenges for common-mode (CM) conducted emissions behavior that can also negatively affect the gate drive design. This dissertation leverages a decomposition technique to derive equivalent models for the differential-mode (DM) and CM behavior for a medium voltage gate driver. A set of DM and CM templates for a generalized two-line system are leveraged with a design procedure to resolve the equivalent models. These models are then mathematically validated in a state-space simulation environment across a wide range of parameter values. Once validated, the models are then analyzed to identify influential parameters that can potentially disrupt the gate-to-source voltage for the high-side switching device. Specifically, the device capacitor network and gate resistor asymmetry are shown to be highly sensitive parameters for the gate-to-source voltage disturbance. The equivalent models are then validated on an empirical evaluation platform across a broad range of configurations. Additionally, a set of empirical studies are carried out to validate the predicted behavior provided in the analysis. The device capacitor ratio has been previously shown to be a sensitive parameter for the gate-to-source voltage, and this is reaffirmed in the empirical studies. The influence of the gate resistors is a unique behavior solely identified by leveraging the DM and CM equivalent models. The gate resistor asymmetry is shown to be a parameter that can be leveraged to increase the reliability of a gate drive design in an otherwise susceptible configuration. Specifically, placing all or most of the gate resistance at the gate node significantly improves the reliability of the gate drive design.